Program – Data from the target images is streamed into the FPGA through its JTAG port. The FPGA then programs this data into the connected flash(s). Multiple files can be specified and programmed at defined offsets. This step can be bypassed if only verification is required.
Example time: 6.2 s (limited by the programming speed of the device).
Verify – The verification checks every byte in the flash against the specified file(s), ensuring there are no data bit errors. This step can be bypassed if only programming or erasing is required.
Example time: 1.8 s with TCK at 10 MHz, reducing to 1.3 s with TCK at 20 MHz.
These example times are provided for a Spartan-6 XC6SLX9 programming a 2 MByte pseudorandom data file into the FPGA’s SPI configuration PROM.