XJFlash

XJFlash is an FPGA-based advanced and innovative method that uses JTAG for high-speed in-system programming (ISP) of flash memories – all serial and parallel flash devices are supported. The most common use of XJFlash is programming the SPI/QSPI NOR flash used to configure an FPGA.

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Key Benefits

With XJFlash you can use the FPGA on your board to achieve flash programming speeds up to 50 times faster than those possible using conventional boundary scan techniques, often reaching the maximum speed for the flash memory.

  • Cuts flash programming times
  • SPI, QSPI, parallel NOR flash devices supported
  • Support for NAND flash devices available on request
  • Shortens development cycles
  • No need for additional equipment
  • Can be used for fast firmware upgrade
  • No FPGA development required

Test Integration

XJFlash programming can be easily integrated into your XJTAG test system using XJDeveloper. All XJFlash programming can be run as part of an XJRunner boundary scan test project.

Configurable Flash Programming

It doesn’t matter whether you need to program a single flash memory device, or multiple devices that are connected in series, to expand the address space, or in parallel, to make a wider data bus, you can use XJFlash to speed up your programming operations.

Custom development

XJFlash can also be used for standalone programming requirements including direct access to I²C and SPI busses or custom protocols such as Microchips ICSP.

The required connections do not need to come from an FPGA on the target board. Providing the protocol signals are available on a header on that board, it should be possible to use XJFlash to achieve fast programming as part of an XJTAG solution.

XJFlash Example Timings

XJFlash will automatically step through four stages each time a flash device is programmed:

Initialisation – The FPGA connected to the flash is configured with the XJFlash image required for the target board.

Example time: 2.1 s.

Erase – The flash can be erased using one of two algorithms. The basic erase will simply erase all blocks within a defined range (this may be the whole flash or just the space needed for the image to be programmed). The more intelligent erase will use the fact that it is quicker to read the flash than to erase it; as such it reads from each address and only starts erasing if some data is found. This step can be skipped if it is known that the flash will always be blank before it is programmed.
Example time – intelligent erase enabled: 0.9 s with a device already erased, to 23 s with a fully programmed device (limited by erase time of device).

Minimum theoretical time for conventional boundary scan: 35 minutes.
Total XJFlash run time: 10.5 s to 32.6 s.

Program – Data from the target images is streamed into the FPGA through its JTAG port. The FPGA then programs this data into the connected flash(s). Multiple files can be specified and programmed at defined offsets. This step can be bypassed if only verification is required.
Example time: 6.2 s (limited by the programming speed of the device).

Verify – The verification checks every byte in the flash against the specified file(s), ensuring there are no data bit errors. This step can be bypassed if only programming or erasing is required.
Example time: 1.8 s with TCK at 10 MHz, reducing to 1.3 s with TCK at 20 MHz.

These example times are provided for a Spartan-6 XC6SLX9 programming a 2 MByte pseudorandom data file into the FPGA’s SPI configuration PROM.

André De Ceuninck

André De Ceuninck

Software Quality | Testing | Certification

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